Presentation 2012-06-22
An Evaluation of Low Power BIST Method
Yasuo SATO, Senling WANG, Takaaki KATO, Kohei MIYASE, Seiji KAJIHARA,
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Abstract(in English) Low-power test technology has been investigated deeply to achieve an accurate and efficient testing. Although many sophisticated methods are proposed for scan-test, there are not so many for logic BIST because of its uncontrollable randomness. However, logic BIST currently becomes vital for system debug or field test. This paper proposes a novel low power BIST technology that eliminates the specified high-frequency parts of vectors in scan-shift and also reduces capture power. The authors show that the proposed technology not only reduces test power but also controls test power with little loss of test coverage.
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Keyword(in English) Logic BIST / Test power / Fault coverage
Paper # DC2012-14
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Committee DC
Conference Date 2012/6/15(1days)
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Paper Information
Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) An Evaluation of Low Power BIST Method
Sub Title (in English)
Keyword(1) Logic BIST
Keyword(2) Test power
Keyword(3) Fault coverage
1st Author's Name Yasuo SATO
1st Author's Affiliation Kyushu Institute of Technology:Japan Science and Technology Agency, CREST()
2nd Author's Name Senling WANG
2nd Author's Affiliation Kyushu Institute of Technology:Japan Science and Technology Agency, CREST
3rd Author's Name Takaaki KATO
3rd Author's Affiliation Kyushu Institute of Technology:Japan Science and Technology Agency, CREST
4th Author's Name Kohei MIYASE
4th Author's Affiliation Kyushu Institute of Technology:Japan Science and Technology Agency, CREST
5th Author's Name Seiji KAJIHARA
5th Author's Affiliation Kyushu Institute of Technology:Japan Science and Technology Agency, CREST
Date 2012-06-22
Paper # DC2012-14
Volume (vol) vol.112
Number (no) 102
Page pp.pp.-
#Pages 6
Date of Issue