Information and Systems-Dependable Computing(Date:2007/11/15)

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[Date]2007/11/15
[Paper #]
目次

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[Date]2007/11/15
[Paper #]
Comparison between STA and SSTA Results in Microprocessor Design

Noriyuki ITO,  Hiroaki KOMATSU,  Hiroyuki SUGIYAMA,  Naomi BIZEN,  Katsumi IGUCHI,  Yuji YOSHIDA,  

[Date]2007/11/15
[Paper #]VLD2007-89,DC2007-44
A New Technique for Elimination of Irregular Data in Measured Values : A Data Screening Technique Appling Skewness of Basic Statistic

Shin-ichi OHKAWA,  Hiroo MASDA,  

[Date]2007/11/15
[Paper #]VLD2007-90,DC2007-45
A Study of Grid-Based Modeling of Spatially Correlated Manufacturing Variability for SSTA

Shinyu NINOMIYA,  Masanori HASHIMOTO,  

[Date]2007/11/15
[Paper #]VLD2007-91,DC2007-46
A Highly Extensible Base Processor for Short-term ASIP Design

Hirofumi IWATO,  Takuji HIEDA,  Hiroaki TANAKA,  Jun SATO,  Keishi SAKANUSHI,  Yoshinori TAKEUCHI,  Masaharu IMAI,  

[Date]2007/11/15
[Paper #]VLD2007-92,DC2007-47
Complexities and Algorithms of Minimum-Delay Compensation Problems in Datapath Synthesis

Keisuke INOUE,  Mineo KANEKO,  Tsuyoshi IWAGAKI,  

[Date]2007/11/15
[Paper #]VLD2007-93,DC2007-48
A Schedule Improvement with Skew Control in Datapath Synthesis

Takayuki OBATA,  Mineo KANEKO,  

[Date]2007/11/15
[Paper #]VLD2007-94,DC2007-49
Necessary and Sufficient Conditions for Symmetry Placements

Kunihiro FUJIYOSHI,  Chikaaki KODAMA,  Shinichi KODA,  

[Date]2007/11/15
[Paper #]VLD2007-95,DC2007-50
Improved Method of Rectilinear Block Packing Based on O-Tree Representation

Hidehiko UKIBE,  Kunihiro FUJIYOSHI,  

[Date]2007/11/15
[Paper #]VLD2007-96,DC2007-51
Synthesis of parallel prefix adders based on Ling's carry computation

Taeko MATSUNAGA,  Shinji KIMURA,  Yusuke MATSUNAGA,  

[Date]2007/11/15
[Paper #]VLD2007-97,DC2007-52
An Efficient Behavioral Synthesis Method Considering Specialized Functional Units

Tsuyoshi SADAKATA,  Yusuke MATSUNAGA,  

[Date]2007/11/15
[Paper #]VLD2007-98,DC2007-53
A Hardware Engine for Generation Deformed Map

Akira ARAHATA,  Ryuta NARA,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2007/11/15
[Paper #]VLD2007-99,DC2007-54
An LDPC Decoder Based on the Min-Sum Algorithm for High Speed WLAN Systems

Nozomu HAMA,  Hiroyuki SHIMAJIRI,  Takeo YOSHIDA,  

[Date]2007/11/15
[Paper #]VLD2007-100,DC2007-55
Area Recovery under Depth Constraint by Cut Substitution for Technology Mapping for LUT-based FPGAs

Taiga TAKATA,  Yusuke MATSUNAGA,  

[Date]2007/11/15
[Paper #]VLD2007-101,DC2007-56
Cycle Partitioned Scheduling for Code Optimization of VLIW DSP

Yuki MASUI,  Nagisa ISHIURA,  

[Date]2007/11/15
[Paper #]VLD2007-102,DC2007-57
Retargetable Linear Assembler for VLIW Processor

Satoshi NOGAITO,  Nagisa ISHIURA,  Masaharu IMAI,  

[Date]2007/11/15
[Paper #]VLD2007-103,DC2007-58
Memory Assignment Method Considering Orders of Operands for Massively Parallel Fine-grained SIMD Processor

Akira KOBASHI,  Ittetsu TANIGUCHI,  Hiroaki TANAKA,  Keishi SAKANUSHI,  Yoshinori TAKEUCHI,  Masaharu IMAI,  Kiyoshi NAKATA,  

[Date]2007/11/15
[Paper #]VLD2007-104,DC2007-59
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[Date]2007/11/15
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[Date]2007/11/15
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