Presentation 2007-11-22
An LDPC Decoder Based on the Min-Sum Algorithm for High Speed WLAN Systems
Nozomu HAMA, Hiroyuki SHIMAJIRI, Takeo YOSHIDA,
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Abstract(in English) In this paper, we show an architecture of low density parity check (LDPC) decoders based on the Min-Sum algorithm for high speed WLAN systems. The decoder supports twelve combinations of code lengths 648, 1296, 1944 bits and code rates 1/2, 2/3, 3/4, 5/6 based on IEEE 802.11n standard. The total cell area of our decoder is 69,467,024 [nm^2].
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Keyword(in English) LDPC Code / IEEE 802.11n / Decoder / Min-Sum Algorithm / WLAN
Paper # VLD2007-100,DC2007-55
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Committee DC
Conference Date 2007/11/15(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
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Title (in English) An LDPC Decoder Based on the Min-Sum Algorithm for High Speed WLAN Systems
Sub Title (in English)
Keyword(1) LDPC Code
Keyword(2) IEEE 802.11n
Keyword(3) Decoder
Keyword(4) Min-Sum Algorithm
Keyword(5) WLAN
1st Author's Name Nozomu HAMA
1st Author's Affiliation Department of Information Engineering, Faculty of Engineering, University of the Ryukyus()
2nd Author's Name Hiroyuki SHIMAJIRI
2nd Author's Affiliation Department of Information Engineering, Faculty of Engineering, University of the Ryukyus
3rd Author's Name Takeo YOSHIDA
3rd Author's Affiliation Department of Information Engineering, Faculty of Engineering, University of the Ryukyus
Date 2007-11-22
Paper # VLD2007-100,DC2007-55
Volume (vol) vol.107
Number (no) 339
Page pp.pp.-
#Pages 6
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