Presentation | 2007-11-22 Retargetable Linear Assembler for VLIW Processor Satoshi NOGAITO, Nagisa ISHIURA, Masaharu IMAI, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | This paper proposes a retargetable linear assembler as a software development tool for custom VLIW processors. The retargetable linear assembler takes a linear assembly program, which can be coded without the detailed knowledge of the microarchitecture, and architecture description of a target processor, to generate an assembly code optimized for the processor. We present an architecture model and the formulation of the scheduling problem for the retargetable linear assembler. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | retargetable linear assembler / VLIW processor / code scheduling |
Paper # | VLD2007-103,DC2007-58 |
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Committee | DC |
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Conference Date | 2007/11/15(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Registration To | Dependable Computing (DC) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Retargetable Linear Assembler for VLIW Processor |
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Keyword(1) | retargetable linear assembler |
Keyword(2) | VLIW processor |
Keyword(3) | code scheduling |
1st Author's Name | Satoshi NOGAITO |
1st Author's Affiliation | Kwansei Gakuin University() |
2nd Author's Name | Nagisa ISHIURA |
2nd Author's Affiliation | Kwansei Gakuin University |
3rd Author's Name | Masaharu IMAI |
3rd Author's Affiliation | Osaka University |
Date | 2007-11-22 |
Paper # | VLD2007-103,DC2007-58 |
Volume (vol) | vol.107 |
Number (no) | 339 |
Page | pp.pp.- |
#Pages | 6 |
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