Presentation | 2007-11-22 Cycle Partitioned Scheduling for Code Optimization of VLIW DSP Yuki MASUI, Nagisa ISHIURA, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | This paper proposes a cycle partitioned scheduling method for code optimization of VLIW DSPs. The previously proposed optimum code scheduling method for VLIW DSPs, which takes into account the capacity of registerfiles, insertion of data transfer operations, and operand asymmetry of functional units, required such an enormous computation cost that it can not handle large scale codes within a practical amount of time. Instead of processing a whole code at a time, our scheduler builds up entire scheduling by repeating computation for a fixed amount of cycles. This curbs the computation cost for each stage and allows optimization of the larger codes within feasible time, though the optimalty of the solution may not be guaranteed. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | clutered VLIW DSP / code optimization / TMS320C62x / cycle partitioned scheduling |
Paper # | VLD2007-102,DC2007-57 |
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Conference Information | |
Committee | DC |
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Conference Date | 2007/11/15(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Dependable Computing (DC) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Cycle Partitioned Scheduling for Code Optimization of VLIW DSP |
Sub Title (in English) | |
Keyword(1) | clutered VLIW DSP |
Keyword(2) | code optimization |
Keyword(3) | TMS320C62x |
Keyword(4) | cycle partitioned scheduling |
1st Author's Name | Yuki MASUI |
1st Author's Affiliation | Kwansei Gakuin University() |
2nd Author's Name | Nagisa ISHIURA |
2nd Author's Affiliation | Kwansei Gakuin University |
Date | 2007-11-22 |
Paper # | VLD2007-102,DC2007-57 |
Volume (vol) | vol.107 |
Number (no) | 339 |
Page | pp.pp.- |
#Pages | 6 |
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