Presentation | 2007-11-22 Area Recovery under Depth Constraint by Cut Substitution for Technology Mapping for LUT-based FPGAs Taiga TAKATA, Yusuke MATSUNAGA, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | In this paper we present the post-processing algorithm, Cut Substitution, for technology mapping for LUT-based FPGAs to minimize the area under depth minimum constraint. The problem to generate a LUT network whose area is minimum under depth minimum costraint seems to be very difficult. Cut Substitution is the process to generate a local optimum solution by eliminating redundant LUTs while the depth of LUT network is maintained. The experiments shows that the proposed method derives LUT networks whose number of LUTs are smaller than the number of LUTs of network which are deribed by the existing algorithms. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | EDA / FPGA / Logic Synthesis / Technology Mapping |
Paper # | VLD2007-101,DC2007-56 |
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Committee | DC |
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Conference Date | 2007/11/15(1days) |
Place (in Japanese) | (See Japanese page) |
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Registration To | Dependable Computing (DC) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Area Recovery under Depth Constraint by Cut Substitution for Technology Mapping for LUT-based FPGAs |
Sub Title (in English) | |
Keyword(1) | EDA |
Keyword(2) | FPGA |
Keyword(3) | Logic Synthesis |
Keyword(4) | Technology Mapping |
1st Author's Name | Taiga TAKATA |
1st Author's Affiliation | Graduate School of Information Science and Electrical Engineering, Kyushu University() |
2nd Author's Name | Yusuke MATSUNAGA |
2nd Author's Affiliation | Faculty of Information Science and Electrical Engineering, Kyushu University |
Date | 2007-11-22 |
Paper # | VLD2007-101,DC2007-56 |
Volume (vol) | vol.107 |
Number (no) | 339 |
Page | pp.pp.- |
#Pages | 6 |
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