Information and Systems-Artificial Intelligence and Knowledge-Based Processing(Date:2012/05/22)

Presentation
表紙

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[Date]2012/5/22
[Paper #]
目次

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[Date]2012/5/22
[Paper #]
An Acceleration of a Graph Cut Segmentation with FPGA

Daichi KOBORI,  Tsutomu MARUYAMA,  

[Date]2012/5/22
[Paper #]RECONF2012-1
An Imageing Device Control System

Toru YABUKI,  Yoshiki YAMAGUCHI,  Yuetsu KODAMA,  

[Date]2012/5/22
[Paper #]RECONF2012-2
FPGA implementation of a video-based real-time pupil detection method

Yuma HATANAKA,  Keisuke DOHI,  Kazuhiro NEGI,  Yuichiro SHIBATA,  Kiyoshi OGURI,  

[Date]2012/5/22
[Paper #]RECONF2012-3
A study on memory controller of MuCCRA-3: Dynamically Reconfigurable Processor Array

Toru KATAGIRI,  Kazuei HIRONAKA,  Hideharu AMANO,  

[Date]2012/5/22
[Paper #]RECONF2012-4
Development of a demonstration system for Ultra-low-power FPGA with Fine-Grained Field-Programmable Threshold Voltage Control

Takashi KAWANAMI,  Masakazu HIOKI,  Yohei MATSUMOTO,  Toshiyuki TSUTUMI,  Tadashi NAKAGAWA,  Toshihiro SEKIGAWA,  Hanpei KOIKE,  

[Date]2012/5/22
[Paper #]RECONF2012-5
Optimization of PE Array Interconnection on CMA to reduce configuration data

Rie UNO,  Nobuaki OZAKI,  Hideharu AMANO,  

[Date]2012/5/22
[Paper #]RECONF2012-6
Implementation and Evaluation of FPGA-based Data Compression Hardware of Floating-Point Data-Stream

Tomohiro Ueno,  Yoshiaki Kono,  Kentaro Sano,  Satoru Yamamoto,  

[Date]2012/5/22
[Paper #]RECONF2012-7
An FPGA Implementation for 3-layer Perception with the FDFM Processor Core Approach

Yuki AGOU,  Yasuaki ITO,  Koji NAKANO,  

[Date]2012/5/22
[Paper #]RECONF2012-8
Implementation of Square Root Calculator on Reconfigurable Processor DS-HIE

Takashi UEDA,  Kazuya TANIGAWA,  Tetsuo HIRONAKA,  

[Date]2012/5/22
[Paper #]RECONF2012-9
Scalability Analysis of Tightly-Coupled FPGA-Cluster for Lattice Boltzmann Computation

Yoshiaki KONO,  Kentaro SANO,  Ryotaro CHIBA,  Satoru YAMAMOTO,  

[Date]2012/5/22
[Paper #]RECONF2012-10
Hard error avoidance for TMR module using dynamic relocation in an FPGA

Hiroki TANAKA,  Yoshihiro ICHINOMIYA,  Sadaki USAGAWA,  Motoki AMAGASAKI,  Masahiro IIDA,  Morihiro KUGA,  Toshinori SUEYOSHI,  

[Date]2012/5/22
[Paper #]RECONF2012-11
A Design of an Interconnection System of Modules and a Control Unit of Reconfiguration for Embedded Systems Utilizing Dynamic Reconfiguration

Tomokazu MIZUNO,  Yoshiaki KIDA,  Ryo KAMIDE,  Shin TERADA,  Mitsuyoshi TOKUDA,  Tomonori IZUMI,  

[Date]2012/5/22
[Paper #]RECONF2012-12
An Efficient Fault Detection and Avoidance Technique for FPGA Interconnects

Yuuki NISHITANI,  Kazuki INOUE,  Motoki AMAGASAKI,  Morihiro KUGA,  Masahiro IIDA,  Toshinori SUEYOSHI,  

[Date]2012/5/22
[Paper #]RECONF2012-13
Implementation and evaluation of the AES/ADPCM on STP and FPGA with Behavioral Synthesis

Yukihito ISHIDA,  Seiya SHIBATA,  Yuki ANDO,  Shinya HONDA,  Hiroaki TAKADA,  Masato EDAHIRO,  

[Date]2012/5/22
[Paper #]RECONF2012-14
Implementation of delay control methods for FPGA-based digital DC-DC Converters

Yoshihiko YAMABE,  Kanako NAKASHIMA,  Keisuke DOHI,  Kazuma HAMAWAKI,  Kentaro YAMASHITA,  Kazuhiro KAJIWARA,  Fujio KUROKAWA,  Yuuichiro SHIBATA,  Kiyoshi OGURI,  

[Date]2012/5/22
[Paper #]RECONF2012-15
Development of Application for Heterogeneous Multi-Core Processor

Yusuke KOIZUMI,  Eiichi SASAKI,  Hideharu AMANO,  Ryuichi SAKAMOTO,  Mitaro NAMIKI,  

[Date]2012/5/22
[Paper #]RECONF2012-16
AN FPGA ACCELERATION OF A LEVEL SET SEGMENTATION METHOD

Haruhisa TSUYAMA,  Tsutomu MARUYAMA,  

[Date]2012/5/22
[Paper #]RECONF2012-17
Proposal and Evaluation of Photon Mapping Accelerlater using FPGA

Takuya KUHARA,  Masato YOSHIMI,  Mitsunori MIKI,  

[Date]2012/5/22
[Paper #]RECONF2012-18
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