| Presentation | 2012-05-29 Implementation of delay control methods for FPGA-based digital DC-DC Converters Yoshihiko YAMABE, Kanako NAKASHIMA, Keisuke DOHI, Kazuma HAMAWAKI, Kentaro YAMASHITA, Kazuhiro KAJIWARA, Fujio KUROKAWA, Yuuichiro SHIBATA, Kiyoshi OGURI, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In the context of energy saving, digital controlled switching power supplies have attracted increasing attention. Especially, FPGA implementation of digital control for a DC-DC converter is promising, since it enables high resolution digital Pulse Width Modulation (PWM) to be controlled in a circuit level with high-speed parallel arithmetic. Conventionally, a delay line has been used to implement PWM with a moderate clock frequency. However, this approach needs manual layout to keep the delay linearity and large FPGA areas. In this paper, a novel implementation of FPGA-based PWM focusing on a Serializer-and-Deserializer (SerDes) primitive is proposed. While the use of SerDes primitives reduces required FPGA areas and improves the productivity, it needs high frequency for clock signals partly. Thus, we analyzed these trade-offs empirically from a viewpoint of delay linearity, resource usage, power consumption, productivity, and control accuracy. The evaluation results revealed that the use of SerDes improved the delay linearity, resource usage, and productivity at the cost of a 66 [mW] increase in power consumption. On the other hand, the dynamic characteristics achieved by DC-DC converters with the two approaches were the almost same. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / switching power supply / pulse width modulation / SerDes / delay line |
| Paper # | RECONF2012-15 |
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| Conference Information | |
| Committee | AI |
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| Conference Date | 2012/5/22(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Artificial Intelligence and Knowledge-Based Processing (AI) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Implementation of delay control methods for FPGA-based digital DC-DC Converters |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | switching power supply |
| Keyword(3) | pulse width modulation |
| Keyword(4) | SerDes |
| Keyword(5) | delay line |
| 1st Author's Name | Yoshihiko YAMABE |
| 1st Author's Affiliation | Nagasaki University() |
| 2nd Author's Name | Kanako NAKASHIMA |
| 2nd Author's Affiliation | Nagasaki University |
| 3rd Author's Name | Keisuke DOHI |
| 3rd Author's Affiliation | Nagasaki University |
| 4th Author's Name | Kazuma HAMAWAKI |
| 4th Author's Affiliation | Nagasaki University |
| 5th Author's Name | Kentaro YAMASHITA |
| 5th Author's Affiliation | Nagasaki University |
| 6th Author's Name | Kazuhiro KAJIWARA |
| 6th Author's Affiliation | Nagasaki University |
| 7th Author's Name | Fujio KUROKAWA |
| 7th Author's Affiliation | Nagasaki University |
| 8th Author's Name | Yuuichiro SHIBATA |
| 8th Author's Affiliation | Nagasaki University |
| 9th Author's Name | Kiyoshi OGURI |
| 9th Author's Affiliation | Nagasaki University |
| Date | 2012-05-29 |
| Paper # | RECONF2012-15 |
| Volume (vol) | vol.112 |
| Number (no) | 70 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |