| Presentation | 2012-05-29 An FPGA Implementation for 3-layer Perception with the FDFM Processor Core Approach Yuki AGOU, Yasuaki ITO, Koji NAKANO, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper presents an FPGA implementation of a 3-layer perceptron using the FDFM (Few DSP blocks and Few block RAMs) approach implemented in the Xilinx Virtex-6 family FPGA. In the FDFM approach, multiple processor cores with few DSP slices and few block RAMs are used. We have implemented 150 processor cores for perceptrons in a Xilinx Virtex-6 family FPGA XC6VLX240T-FF1156. The implementation results show that the 150 processor cores for 32-32-32 input-hidden-output layer perceptrons can be implemented in the FPGA using 150 DSP48 slices, 185 block RAMs, and 9676 slices. It runs in 242.89MHz clock frequency and a single evaluation of 150 nodes perceptron can be performed 1.65 × 10^7 times per second. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Perceptron / Neural networks / FPGA / DSP48 slice / Block RAM / Pipeline |
| Paper # | RECONF2012-8 |
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| Conference Information | |
| Committee | AI |
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| Conference Date | 2012/5/22(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Artificial Intelligence and Knowledge-Based Processing (AI) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An FPGA Implementation for 3-layer Perception with the FDFM Processor Core Approach |
| Sub Title (in English) | |
| Keyword(1) | Perceptron |
| Keyword(2) | Neural networks |
| Keyword(3) | FPGA |
| Keyword(4) | DSP48 slice |
| Keyword(5) | Block RAM |
| Keyword(6) | Pipeline |
| 1st Author's Name | Yuki AGOU |
| 1st Author's Affiliation | Department of Information Engineering, Hiroshima University() |
| 2nd Author's Name | Yasuaki ITO |
| 2nd Author's Affiliation | Department of Information Engineering, Hiroshima University |
| 3rd Author's Name | Koji NAKANO |
| 3rd Author's Affiliation | Department of Information Engineering, Hiroshima University |
| Date | 2012-05-29 |
| Paper # | RECONF2012-8 |
| Volume (vol) | vol.112 |
| Number (no) | 70 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |