| Presentation | 2012-05-30 AN FPGA ACCELERATION OF A LEVEL SET SEGMENTATION METHOD Haruhisa TSUYAMA, Tsutomu MARUYAMA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, we propose a new level set algorithm for real-time image segmentation, and its FPGA implementation. Our algorithm is designed so that high performance can be achieved on hardware platforms by simplifying the memory access sequence. For simplifying the memory access sequence, more computation is required than previous algorithms, but its performance on FPGA is fast enough for real-time applications. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | image processing / image segmentation / level set / FPGA |
| Paper # | RECONF2012-17 |
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| Conference Information | |
| Committee | AI |
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| Conference Date | 2012/5/22(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Paper Information | |
| Registration To | Artificial Intelligence and Knowledge-Based Processing (AI) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | AN FPGA ACCELERATION OF A LEVEL SET SEGMENTATION METHOD |
| Sub Title (in English) | |
| Keyword(1) | image processing |
| Keyword(2) | image segmentation |
| Keyword(3) | level set |
| Keyword(4) | FPGA |
| 1st Author's Name | Haruhisa TSUYAMA |
| 1st Author's Affiliation | University of Tsukuba() |
| 2nd Author's Name | Tsutomu MARUYAMA |
| 2nd Author's Affiliation | University of Tsukuba |
| Date | 2012-05-30 |
| Paper # | RECONF2012-17 |
| Volume (vol) | vol.112 |
| Number (no) | 70 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |