Presentation 2012-05-29
A study on memory controller of MuCCRA-3: Dynamically Reconfigurable Processor Array
Toru KATAGIRI, Kazuei HIRONAKA, Hideharu AMANO,
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Abstract(in English) In order to achieve a high performance on the Dynamically Reconfigurable Processor Array(DRPA), it is necessary to use PEs effectively. However, a prototype DRPA, MuCCRA-3 needs to generate read/write addresses for accessing data memories, and counts a number of loops on PEs. Hence, PEs of MuCCRA-3 can not be used effectively for actual processing of applications. To solve this problem and improve performance. We extend the memory controller of MuCCRA-3 and named it MuCCRA-3-EXMC. PEs of MuCCRA-3-EXMC can be concen-trated on executing the actual processing by the extended memory controller performing address generation and loop count. Evaluation results showed that MuCCRA-3-EXMC can improve its performance by 12~23% and reduce its energy consumption by 9~20% without a large increase of its area.
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Keyword(in English) Dynamically Reconfigurable Processor Array / Accelerator / Memory Controller
Paper # RECONF2012-4
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Committee AI
Conference Date 2012/5/22(1days)
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Registration To Artificial Intelligence and Knowledge-Based Processing (AI)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A study on memory controller of MuCCRA-3: Dynamically Reconfigurable Processor Array
Sub Title (in English)
Keyword(1) Dynamically Reconfigurable Processor Array
Keyword(2) Accelerator
Keyword(3) Memory Controller
1st Author's Name Toru KATAGIRI
1st Author's Affiliation Graduate School of Science and Technology, Keio University()
2nd Author's Name Kazuei HIRONAKA
2nd Author's Affiliation Graduate School of Science and Technology, Keio University
3rd Author's Name Hideharu AMANO
3rd Author's Affiliation Graduate School of Science and Technology, Keio University
Date 2012-05-29
Paper # RECONF2012-4
Volume (vol) vol.112
Number (no) 70
Page pp.pp.-
#Pages 6
Date of Issue