Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2010/01/19)

Presentation
Effective Hardware Task Context Switching in Virtex-4 FPGAs

Krzysztof Jozwik,  Hiroyuki Tomiyama,  Shinya Honda,  Hiroaki Takada,  

[Date]2010/1/19
[Paper #]VLD2009-87,CPSY2009-69,RECONF2009-72
Hardware Acceleration in a Scalable FPGA System

Hironori NAKAJO,  Ryuichi SAKAMOTO,  

[Date]2010/1/19
[Paper #]VLD2009-88,CPSY2009-70,RECONF2009-73
Expansion of Hardware in a Scalable FPGA System

Hironori NAKAJO,  Takefumi MIYOSHI,  Satoshi FUNADA,  Ryuichi SAKAMOTO,  

[Date]2010/1/19
[Paper #]VLD2009-89,CPSY2009-71,RECONF2009-74
An efficient hardware-oriented algorithm for regular expression matching based on parallel bit-distribution

Yusaku KANETA,  Shingo YOSHIZAWA,  Shin-ichi MINATO,  Hiroki ARIMURA,  Yoshikazu MIYANAGA,  

[Date]2010/1/19
[Paper #]VLD2009-90,CPSY2009-72,RECONF2009-75
Regular Expression Pattern Matching Hardware for Realizing Iteration of Strings Using Quantifiers

Yoichi WAKABA,  Shin'ichi WAKABAYASHI,  Shinobu NAGAYAMA,  Masato INAGI,  

[Date]2010/1/19
[Paper #]VLD2009-91,CPSY2009-73,RECONF2009-76
A Packet Classifier Using a Parallel Branching Program Machine

Hiroki NAKAHARA,  Tsutomu SASAO,  Munehiro MATSUURA,  Yoshifumi KAWAMURA,  

[Date]2010/1/19
[Paper #]VLD2009-92,CPSY2009-74,RECONF2009-77
An Implementation of Fail-soft Systems with Adaptive Fault Tolerance using SRAM-based FPGAs

Satoshi FUJIE,  Ryoji NOJI,  Yuki YOSHIKAWA,  Hideyuki ICHIHARA,  Tomoo INOUE,  

[Date]2010/1/19
[Paper #]VLD2009-93,CPSY2009-75,RECONF2009-78
Fault Recovery Technique for Softcore Processor using Partial Reconfiguration

Yoshihiro ICHINOMIYA,  Shiro TANOUE,  Motoki AMAGASAKI,  Morihiro KUGA,  Toshinori SUEYOSHI,  

[Date]2010/1/19
[Paper #]VLD2009-94,CPSY2009-76,RECONF2009-79
An Estimation Method of Delay Time Variation by Crosstalk in Logic Circuit Level

Masayuki KOBAYASHI,  Wataru SENTO,  Masahiko TOYONAGA,  Michiaki MURAOKA,  

[Date]2010/1/19
[Paper #]VLD2009-95,CPSY2009-77,RECONF2009-80
A remote dynamic optically reconfigurable gate array using a fiber array

Yumiko UENO,  Minoru WATANABE,  

[Date]2010/1/19
[Paper #]VLD2009-96,CPSY2009-78,RECONF2009-81
Compensation method for photodiode characteristics variation using an analog configuration context

Yuji AOYAMA,  Minoru WATANABE,  

[Date]2010/1/19
[Paper #]VLD2009-97,CPSY2009-79,RECONF2009-82
A programmable optically reconfigurable gate array with a silver-halide holographic memory

Shinya KUBOTA,  Minoru WATANABE,  

[Date]2010/1/19
[Paper #]VLD2009-98,CPSY2009-80,RECONF2009-83
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