| Presentation | 2010-01-27 Effective Hardware Task Context Switching in Virtex-4 FPGAs Krzysztof Jozwik, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A unique aspect of flexibility provided by some of the FPGAs such as Xilinx Virtex-4 family is the capability of dynamic and partial reconfiguration, giving them additional leverage over the other co-existing FPGA solutions by allowing implementation of such concepts as a hardware task. When compared to classical software task effective employment of the new idea in preemptive multitasking systems poses many difficulties and involves many mechanisms such as context saving and restoring, to be built practically from the scratch. This paper presents an effective approach to high-speed context switching for Virtex4-based DPR (Dynamic Partial Reconfiguration) Systems based on developed embedded system infrastructure with lightweight control bus, enhancing management of reconfigurable hardware modules and very efficient, instruction-driven reconfigurationlreadback controller which offers 78-fold speed-ups and further superior functionalities when compared to baseline IP provided by FPGA's manufacturer. The whole system is additionally supported by developed bitstream manipulation tool intended for PC (Personal Computer) and used as a back-end program for current DPR design flow. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / Dynamic Partial Reconfiguration / HW Context-switch |
| Paper # | VLD2009-87,CPSY2009-69,RECONF2009-72 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2010/1/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Effective Hardware Task Context Switching in Virtex-4 FPGAs |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | Dynamic Partial Reconfiguration |
| Keyword(3) | HW Context-switch |
| 1st Author's Name | Krzysztof Jozwik |
| 1st Author's Affiliation | Graduate School of Information Science, Nagoya University() |
| 2nd Author's Name | Hiroyuki Tomiyama |
| 2nd Author's Affiliation | Graduate School of Information Science, Nagoya University |
| 3rd Author's Name | Shinya Honda |
| 3rd Author's Affiliation | Graduate School of Information Science, Nagoya University |
| 4th Author's Name | Hiroaki Takada |
| 4th Author's Affiliation | Graduate School of Information Science, Nagoya University |
| Date | 2010-01-27 |
| Paper # | VLD2009-87,CPSY2009-69,RECONF2009-72 |
| Volume (vol) | vol.109 |
| Number (no) | 393 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |