Presentation 2010-01-27
Expansion of Hardware in a Scalable FPGA System
Hironori NAKAJO, Takefumi MIYOSHI, Satoshi FUNADA, Ryuichi SAKAMOTO,
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Abstract(in English) Currently, in a field of high performance computing, some FPGAs are utilized to accelerate processing against some formalized algorithms which need a vast amount of calculations. However, due to the limitation of FPGA capacity, in order to implement a large size of circuits, a mechanism to implement a logical single large circuit using fast serial links among many FPGAs is necessary. In this paper, we propose a mechanism to expand hardware in the Scalable FPGA system which has been currently developed. We discuss its feasibility to expand a hardware circuit with the mechanism as well as future evolutions.
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Keyword(in English) FPGA / partioning circuits / fast serial communication
Paper # VLD2009-89,CPSY2009-71,RECONF2009-74
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Committee VLD
Conference Date 2010/1/19(1days)
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Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Expansion of Hardware in a Scalable FPGA System
Sub Title (in English)
Keyword(1) FPGA
Keyword(2) partioning circuits
Keyword(3) fast serial communication
1st Author's Name Hironori NAKAJO
1st Author's Affiliation Institute of Symbio-technology, Tokyo University of Agriculture and Technology()
2nd Author's Name Takefumi MIYOSHI
2nd Author's Affiliation Department of Computer Science Tokyo Institute of Technology Graduate School of Information Science and Engineering
3rd Author's Name Satoshi FUNADA
3rd Author's Affiliation e-trees.Japan, Inc
4th Author's Name Ryuichi SAKAMOTO
4th Author's Affiliation Faculty of Engineering Tokyo University of Agriculture and Technology
Date 2010-01-27
Paper # VLD2009-89,CPSY2009-71,RECONF2009-74
Volume (vol) vol.109
Number (no) 393
Page pp.pp.-
#Pages 6
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