Presentation 2010-01-27
An Estimation Method of Delay Time Variation by Crosstalk in Logic Circuit Level
Masayuki KOBAYASHI, Wataru SENTO, Masahiko TOYONAGA, Michiaki MURAOKA,
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Abstract(in English) In this paper, a method which detects crosstalk points and timing error points by using the logic simulation with the back annotation of the delay time equation of crosstalk is proposed. The conventional method analyzed crosstalk with the static timing analysis and the circuit simulator. However, this method calculates the delay time increase of crosstalk by the delay time equation and can detect crosstalk points by using the logic simulation with the back annotation of the delay time. Furthermore, this method is able to detect crosstalk points which generate timing errors.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Crosstalk / Design Methodology / Logic Simulation / EDA / CAD
Paper # VLD2009-95,CPSY2009-77,RECONF2009-80
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Committee VLD
Conference Date 2010/1/19(1days)
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Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) An Estimation Method of Delay Time Variation by Crosstalk in Logic Circuit Level
Sub Title (in English)
Keyword(1) Crosstalk
Keyword(2) Design Methodology
Keyword(3) Logic Simulation
Keyword(4) EDA
Keyword(5) CAD
1st Author's Name Masayuki KOBAYASHI
1st Author's Affiliation Information Science Division, Graduate School of Science, Kochi University()
2nd Author's Name Wataru SENTO
2nd Author's Affiliation Faculty of Science, Kochi University
3rd Author's Name Masahiko TOYONAGA
3rd Author's Affiliation Information Science Division, Graduate School of Science, Kochi University
4th Author's Name Michiaki MURAOKA
4th Author's Affiliation Information Science Division, Graduate School of Science, Kochi University
Date 2010-01-27
Paper # VLD2009-95,CPSY2009-77,RECONF2009-80
Volume (vol) vol.109
Number (no) 393
Page pp.pp.-
#Pages 6
Date of Issue