Electronics-Integrated Circuits and Devices(Date:2006/08/10)

Presentation
Experimental Study on Breakdown of Mobility Universality in <100>-Directed (110)-Oriented pMOSFETs

Ken SHIMIZU,  Takuya SARAYA,  Toshiro HIRAMOTO,  

[Date]2006/8/10
[Paper #]SDM2006-143,ICD2006-97
Parameter and Random Dopant Fluctuation on Fully-Depleted SOI MOSFETs with a Very Thin BOX

Tetsu OHTOU,  Nobuyuki SUGII,  Toshiro HIRAMOTO,  

[Date]2006/8/10
[Paper #]SDM2006-144,ICD2006-98
Suppression effects of threshold voltage variation of Ni FUSI gate electrode for 45nm node and beyond LSTP and SRAM devices

Y. Okayama,  T. Saito,  A. Oishi,  K. Nakajima,  Taniguchi S. /,  T. Ono,  K. Nakayama,  R. Watanabe,  A. Eiho,  T. Komoda,  T. Kimura,  M. Hamaguchi,  Y. Takegawa,  T. Aoyama,  T. Iinuma,  K. Fukasaku,  R. Morimoto,  K. Oshima,  K. Oono,  M. Saito,  M. Iwai,  S. Yamada,  N. Nagashima,  F. Matsuoka,  

[Date]2006/8/10
[Paper #]SDM2006-145,ICD2006-99
High Performance Dual Metal Gate CMOS with High Mobility and Low Threshold Voltage Applicable to Bulk CMOS Technology

S. Yamaguchi,  K. Tai,  T. Hirano,  T. Ando,  S. Hiyama,  J. Wang,  Y. Hagimoto,  Y. Nagahama,  T. Kato,  K. Nagano,  M. Yamanaka,  S. Terauchi,  S. Kanda,  R. Yamamoto,  Y. Tateshita,  Y. Tagawa,  H. Iwamoto,  M. Saito,  N. Nagashima,  S. Kadomura,  

[Date]2006/8/10
[Paper #]SDM2006-146,ICD2006-100
Embedded Bulk-FinFET SRAM Cell Technology with Bulk Planar FET Peripheral Circuit for hp32nm node and beyond

H. Kawasaki,  S. Inaba,  K. Okano,  A. Kaneko,  A. Yagishita,  T. Izumida,  T. Kanemura,  T. Sasaki,  N. Ohtsuka,  N. Aoki,  K. Suguro,  K. Eguchi,  Y. Tsunashima,  K. Ishimaru,  H. Ishiuchi,  

[Date]2006/8/10
[Paper #]SDM2006-147,ICD2006-101
A 65nm Ultra-High-Density Dual-port SRAM with 0.71um^2 8T-cell for SoC

S. Imaoka,  K. Nii,  Y. Masuda,  M. Yabuuchi,  Y. Tsukamoto,  S. Ohbayashi,  M. Igarashi,  K. Tomita,  N. Tsuboi,  H. Makino,  K. Ishibashi,  H. Shinohara,  

[Date]2006/8/10
[Paper #]SDM2006-148,ICD2006-102
A Stable SRAM Cell Design Against Simultaneously R/W Disturbed Accesses

Toshikazu SUZUKI,  Hiroyuki YAMAUCHI,  Yoshinobu YAMAGAMI,  Katsuji SATOMI,  Hironori AKAMATSU,  

[Date]2006/8/10
[Paper #]SDM2006-149,ICD2006-103
Deep Pipelined SRAM Design for High Performance Processor

Toru ASANO,  

[Date]2006/8/10
[Paper #]SDM2006-150,ICD2006-104
A 65nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits

Makoto YABUUCHI,  Shigeki OHBAYASHI,  Koji NII,  Yasumasa TSUKAMOTO,  Susumu IMAOKA,  Motoshige IGARASHI,  Masahiko TAKEUCHI,  Hiroshi KAWASHIMA,  Hiroshi MAKINO,  Yasuo YAMAGUCHI,  Kazuhiro TSUKAMOTO,  Masahide INUISHI,  Koichiro ISHIBASHI,  Hirofumi SHINOHARA,  

[Date]2006/8/10
[Paper #]SDM2006-151,ICD2006-105
A Vth-Variation-Tolerant SRAM with 0.3-V Minimum Operation Voltage for Memory-Rich SoC under DVS Environment

Hiroki NOGUCHI,  Yasuhiro MORITA,  Hidehiro FUJIWARA,  Kentaro KAWAKAMI,  Junichi MIYAKOSHI,  Shinji MIKAMI,  Koji NII,  Hiroshi KAWAGUCHI,  Masahiko YOSHIMOTO,  

[Date]2006/8/10
[Paper #]SDM2006-152,ICD2006-106
The Impact of Random Telegraph Signals on the Scaling of Multilevel Flash Memories

Hideaki KURATA,  Kazuo OTSUGA,  Akira KOTABE,  Shinya KAJIYAMA,  Taro OSABE,  Yoshitaka SASAGO,  Shunichi NARUMI,  Kenji TOKAMI,  Shiro KAMOHARA,  Osamu TSUCHIYA,  

[Date]2006/8/10
[Paper #]SDM2006-153,ICD2006-107
SRAM : challenges to lower operating voltage and higher immunity for characteristic variation

Toshiro Hiramoto,  Satoshi Inaba,  Kenji Noda,  Yasuhiro Sanbonsugi,  Atsushi Kawasumi,  Kiyoshi Takeuchi,  Masanao Yamaoka,  

[Date]2006/8/10
[Paper #]SDM2006-154,ICD2006-108
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