| Presentation | 2006-08-18 Deep Pipelined SRAM Design for High Performance Processor Toru ASANO, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Processor performance depends strongly upon SRAM performance. In deep sub-micron technology, increasing device performance does not always solve timing problem due to wire delay. Multiple processor core architecture gives a new challenge for SRAM designer such as macro size which affects to total chip size by multiple factor. In such circumstances, SRAM designers need to find the best implementation of memory function to silicon with architects, logic designers, and integrators. The design approach to maximize performance in full custom chip design will be discussed. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | pipelined SRAM / embedded SRAM / high performance |
| Paper # | SDM2006-150,ICD2006-104 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2006/8/10(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Deep Pipelined SRAM Design for High Performance Processor |
| Sub Title (in English) | |
| Keyword(1) | pipelined SRAM |
| Keyword(2) | embedded SRAM |
| Keyword(3) | high performance |
| 1st Author's Name | Toru ASANO |
| 1st Author's Affiliation | IBM Japan, Ltd() |
| Date | 2006-08-18 |
| Paper # | SDM2006-150,ICD2006-104 |
| Volume (vol) | vol.106 |
| Number (no) | 207 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |