Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2024/02/28)

Presentation
Research on Routing Method for Spacer-Is-Metal Type Self-Aligned Double Patterning

Koki Tanaka(TUAT),  Takuto Amari(TUAT),  Kunihiro Fujiyoshi(TUAT),  

[Date]2024-02-28
[Paper #]VLD2023-105,HWS2023-65,ICD2023-94
A Template Routing Method Using SMT Solver for Double Via-Constrained Pair Symmetric Routing Problem

Zuan Jo(Tokyo Tech),  Satoshi Tayu(Tokyo Tech),  Atsushi Takahashi(Tokyo Tech),  Mathieu Molongo(JEDAT),  Makoto Minami(JEDAT),  Katsuya Nishioka(JEDAT),  

[Date]2024-02-28
[Paper #]VLD2023-102,HWS2023-62,ICD2023-91
Three-layer Bottleneck Channel Track Assignment for Pins Placed on Opposite Sides

Kazuya Taniguchi(Tokyo Tech),  Satoshi Tayu(Tokyo Tech),  Atsushi Takahashi(Tokyo Tech),  Mathieu Molongo(Jedat),  Makoto Minami(Jedat),  Katsuya Nishioka(Jedat),  

[Date]2024-02-28
[Paper #]VLD2023-103,HWS2023-63,ICD2023-92
Single Trunk Routing Problem for Generalized Channel

Zezhong Wang(Tokyo Tech),  Masayuki Shimoda(Tokyo Tech),  Atsushi Takahashi(Tokyo Tech),  

[Date]2024-02-28
[Paper #]VLD2023-104,HWS2023-64,ICD2023-93
High Level Datapath Synthesis for Enhanced Timing Tunability

Mineo Kaneko(JAIST),  

[Date]2024-02-28
[Paper #]VLD2023-101,HWS2023-61,ICD2023-90
Set-Pair Routing Solver with Layer-by-layer Formulation on ILP

Yasuhiro Takashima(Univ of Kitakyushu),  

[Date]2024-02-28
[Paper #]VLD2023-100,HWS2023-60,ICD2023-89
解空間内の状態遷移を容易にする冗長符号を活用したQUBO変換手法

Masashi Tawada(Waseda Univ.),  Nozomu Togawa(Waseda Univ.),  

[Date]2024-02-28
[Paper #]VLD2023-99,HWS2023-59,ICD2023-88
Fundamental study on individual identification using electromagnetic characteristics unique to electronic devices

Tsuyoshi Kobayashi(Mitsubishi Electric),  Mio Akahori(Mitsubishi Electric),  Takahiro Horiguchi(Mitsubishi Electric),  

[Date]2024-02-29
[Paper #]VLD2023-114,HWS2023-74,ICD2023-103
[Memorial Lecture] Design of Aging-Robust Clonable PUF Using an Insulator-Based ReRAM for Organic Circuits

Kunihiro Oshima(Kyoto Univ.),  Kazunori Kuribara(AIST),  Takashi Sato(Kyoto Univ.),  

[Date]2024-02-29
[Paper #]VLD2023-116,HWS2023-76,ICD2023-105
Design of RISC-V SoC with Post-quantum Cryptographic Algorithm Acceleration

Jiyuan Xin(UTokyo),  Makoto Ikeda(UTokyo),  

[Date]2024-02-29
[Paper #]VLD2023-110,HWS2023-70,ICD2023-99
Instruction-set Extension Using Graph Neural Networks

Ayumi Uki(TiTech),  Yuko Hara(TiTech),  

[Date]2024-02-29
[Paper #]VLD2023-107,HWS2023-67,ICD2023-96
[Memorial Lecture] Modeling of Tamper Resistance to Electromagnetic Side-channel Attacks on Voltage-scaled Circuits

Kazuki Minamiguchi(Osaka Univ.),  Yoshihiro Midoh(Osaka Univ.),  Noriyuki Miura(Osaka Univ.),  Jun Shiomi(Osaka Univ.),  

[Date]2024-02-29
[Paper #]VLD2023-117,HWS2023-77,ICD2023-106
[Memorial Lecture] Logic Locking over TFHE for Securing User Data and Algorithms

Kohei Suemitsu(Kyoto Univ.),  Kotaro Matsuoka(Kyoto Univ.),  Takashi Sato(Kyoto Univ.),  Masanori Hashimoto(Kyoto Univ.),  

[Date]2024-02-29
[Paper #]VLD2023-118,HWS2023-78,ICD2023-107
A Study of Edge AI & Distributed DB Computing Architecture for Edge-Centric Digital Twin

Hiroshi Miyata(TAN),  Kazutami Arimoto(Okayama Pref. Univ.),  Atsushi Hayami(TAN),  Hisayoshi Mizuno(TAN),  Tomoyuki Yokogawa(Okayama Pref. Univ.),  

[Date]2024-02-29
[Paper #]VLD2023-111,HWS2023-71,ICD2023-100
自動化フレームワークにより生成されたトロイ回路を対象とした機械学習によるハードウェアトロイ識別の評価

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[Date]2024-02-29
[Paper #]VLD2023-108,HWS2023-68,ICD2023-97
Distributed Task Migration Algorithm for 3D Stacked Chips and Evaluation with actual measurement

Takahiro Kanamori(SIT),  Songxiang Wang(SIT),  Kimiyoshi Usami(SIT),  

[Date]2024-02-29
[Paper #]VLD2023-109,HWS2023-69,ICD2023-98
Nano Artifact Metric Systems Resistant Against Clones Produced by Scanning Probe Lithography

Akira Iwahashi(YNU),  Naoki Yoshida(YNU),  Katsunari Yoshioka(YNU),  Tsutomu Matsumoto(AIST),  

[Date]2024-02-29
[Paper #]VLD2023-113,HWS2023-73,ICD2023-102
[Memorial Lecture] Sparse-Sparse Matrix Multiplication Accelerator on FPGA featuring Distribute-Merge Product Dataflow

Yuta Nagahara(Tokyo Tech),  Jiale Yan(Tokyo Tech),  Kazushi Kawamura(Tokyo Tech),  Masato Motomura(Tokyo Tech),  Thiem Van Chu(Tokyo Tech),  

[Date]2024-02-29
[Paper #]VLD2023-119,HWS2023-79,ICD2023-108
誤り検出符号と振幅分布に着目した漏えい電磁波からのビット列復元に関する基礎検討

Koki Abe(NAIST),  Taiki Kitazawa(NAIST),  Daisuke Fujimoto(NAIST),  Yuichi Hayashi(NAIST),  

[Date]2024-02-29
[Paper #]VLD2023-115,HWS2023-75,ICD2023-104
マルチチップアセンブリにおけるチップ近傍排熱特性の評価と解析

Shuhei Yokota(Kobe Univercity),  Rikuu Hasegawa(Kobe Univercity),  Kazuki Monta(Kobe Univercity),  Takaki Okidono(Kobe Univercity),  Takuji Miki(Kobe Univercity),  Makoto Nagata(Kobe Univercity),  

[Date]2024-02-29
[Paper #]VLD2023-112,HWS2023-72,ICD2023-101
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