| Presentation | 2024-02-29 [Memorial Lecture] Logic Locking over TFHE for Securing User Data and Algorithms Kohei Suemitsu, Kotaro Matsuoka, Takashi Sato, Masanori Hashimoto, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper proposes the application of logic locking over TFHE to protect both user data and algorithms, such as input user data and models in machine learning inference applications. With the proposed secure computation protocol, algorithm evaluation can be performed distributively on honest-but-curious user computers while keeping the algorithm secure. To achieve this, we combine conventional logic locking for untrusted foundries with TFHE to enable secure computation. By encrypting the logic locking key using TFHE, the key is secured with the degree of TFHE. We implemented the proposed secure protocols for combinational logic neural networks and decision trees using LUT-based obfuscation. Regarding the security analysis, we subjected them to the SAT attack and evaluated their resistance based on the execution time. We successfully configured the proposed secure protocol to be resistant to the SAT attack in all machine learning benchmarks. Also, the experimental result shows that the proposed secure computation involved almost no TFHE runtime overhead in a test case with thousands of gates. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | secure computationlogic lockingLUT-based obfuscationTFHE |
| Paper # | VLD2023-118,HWS2023-78,ICD2023-107 |
| Date of Issue | 2024-02-21 (VLD, HWS, ICD) |
| Conference Information | |
| Committee | VLD / HWS / ICD |
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| Conference Date | 2024/2/28(4days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Shigetoshi Nakatake(Univ. of Kitakyushu) / Daisuke Suzuki(Mitsubishi Electric) / Makoto Ikeda(Univ. of Tokyo) |
| Vice Chair | Yuichi Sakurai(Hitachi) / Yuichi Hayashi(NAIST) / Toru Akishita(Sony Semiconductor Solutions) / Hayato Wakabayashi(Sony Semiconductor Solutions) |
| Secretary | Yuichi Sakurai(Socionext) / Yuichi Hayashi(Hirosaki Univ.) / Toru Akishita(Sony Semiconductor Solutions) / Hayato Wakabayashi(AIST) |
| Assistant | Takuma Nishimoto(Hitachi) / / Ryo Shirai(Kyoto Univ.) / Jun Shiomi(Osaka Univ.) / Takeshi Kuboki(Sony Semiconductor Solutions) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Hardware Security / Technical Committee on Integrated Circuits and Devices |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | [Memorial Lecture] Logic Locking over TFHE for Securing User Data and Algorithms |
| Sub Title (in English) | |
| Keyword(1) | secure computationlogic lockingLUT-based obfuscationTFHE |
| 1st Author's Name | Kohei Suemitsu |
| 1st Author's Affiliation | Kyoto University(Kyoto Univ.) |
| 2nd Author's Name | Kotaro Matsuoka |
| 2nd Author's Affiliation | Kyoto University(Kyoto Univ.) |
| 3rd Author's Name | Takashi Sato |
| 3rd Author's Affiliation | Kyoto University(Kyoto Univ.) |
| 4th Author's Name | Masanori Hashimoto |
| 4th Author's Affiliation | Kyoto University(Kyoto Univ.) |
| Date | 2024-02-29 |
| Paper # | VLD2023-118,HWS2023-78,ICD2023-107 |
| Volume (vol) | vol.123 |
| Number (no) | VLD-390,HWS-391,ICD-392 |
| Page | pp.pp.100-100(VLD), pp.100-100(HWS), pp.100-100(ICD), |
| #Pages | 1 |
| Date of Issue | 2024-02-21 (VLD, HWS, ICD) |