Presentation	2024-02-28 High Level Datapath Synthesis for Enhanced Timing Tunability Mineo Kaneko,
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Abstract(in English)
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Keyword(in English)
Paper #	VLD2023-101,HWS2023-61,ICD2023-90
Date of Issue	2024-02-21 (VLD, HWS, ICD)

Conference Information
Committee	VLD / HWS / ICD
Conference Date	2024/2/28(4days)
Place (in Japanese)	(See Japanese page)
Place (in English)
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Topics (in English)
Chair	Shigetoshi Nakatake(Univ. of Kitakyushu) / Daisuke Suzuki(Mitsubishi Electric) / Makoto Ikeda(Univ. of Tokyo)
Vice Chair	Yuichi Sakurai(Hitachi) / Yuichi Hayashi(NAIST) / Toru Akishita(Sony Semiconductor Solutions) / Hayato Wakabayashi(Sony Semiconductor Solutions)
Secretary	Yuichi Sakurai(Socionext) / Yuichi Hayashi(Hirosaki Univ.) / Toru Akishita(Sony Semiconductor Solutions) / Hayato Wakabayashi(AIST)
Assistant	Takuma Nishimoto(Hitachi) / / Ryo Shirai(Kyoto Univ.) / Jun Shiomi(Osaka Univ.) / Takeshi Kuboki(Sony Semiconductor Solutions)

Paper Information
Registration To	Technical Committee on VLSI Design Technologies / Technical Committee on Hardware Security / Technical Committee on Integrated Circuits and Devices
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	High Level Datapath Synthesis for Enhanced Timing Tunability
Sub Title (in English)
Keyword(1)
1st Author's Name	Mineo Kaneko
1st Author's Affiliation	Japan Advanced Institute of Science and Technology(JAIST)
Date	2024-02-28
Paper #	VLD2023-101,HWS2023-61,ICD2023-90
Volume (vol)	vol.123
Number (no)	VLD-390,HWS-391,ICD-392
Page	pp.pp.12-17(VLD), pp.12-17(HWS), pp.12-17(ICD),
#Pages	6
Date of Issue	2024-02-21 (VLD, HWS, ICD)