| Presentation | 2024-02-28 Single Trunk Routing Problem for Generalized Channel Zezhong Wang, Masayuki Shimoda, Atsushi Takahashi, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper addresses the challenges posed by tight horizontal routing capacity in critical layers of chip design. A Generalized Channel Routing Problem (GCRP) is introduced, treating the critical layer as a generalized channel with predefined horizontal tracks. The objective is to efficiently connect all pins of a net by a Single Trunk Steiner Tree in the generalized channel while minimizing vertical congestion. The proposed model accommodates the unique characteristics of modern advanced chips. This paper contributes by formulating the GCRP and presenting a problem-centric perspective on-chip routing, emphasizing the importance of efficient use of critical routing layers. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Global routing / Channel routing problem / Wirelength minimization |
| Paper # | VLD2023-104,HWS2023-64,ICD2023-93 |
| Date of Issue | 2024-02-21 (VLD, HWS, ICD) |
| Conference Information | |
| Committee | VLD / HWS / ICD |
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| Conference Date | 2024/2/28(4days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Shigetoshi Nakatake(Univ. of Kitakyushu) / Daisuke Suzuki(Mitsubishi Electric) / Makoto Ikeda(Univ. of Tokyo) |
| Vice Chair | Yuichi Sakurai(Hitachi) / Yuichi Hayashi(NAIST) / Toru Akishita(Sony Semiconductor Solutions) / Hayato Wakabayashi(Sony Semiconductor Solutions) |
| Secretary | Yuichi Sakurai(Socionext) / Yuichi Hayashi(Hirosaki Univ.) / Toru Akishita(Sony Semiconductor Solutions) / Hayato Wakabayashi(AIST) |
| Assistant | Takuma Nishimoto(Hitachi) / / Ryo Shirai(Kyoto Univ.) / Jun Shiomi(Osaka Univ.) / Takeshi Kuboki(Sony Semiconductor Solutions) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Hardware Security / Technical Committee on Integrated Circuits and Devices |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Single Trunk Routing Problem for Generalized Channel |
| Sub Title (in English) | |
| Keyword(1) | Global routing |
| Keyword(2) | Channel routing problem |
| Keyword(3) | Wirelength minimization |
| 1st Author's Name | Zezhong Wang |
| 1st Author's Affiliation | Tokyo Institute of Technology(Tokyo Tech) |
| 2nd Author's Name | Masayuki Shimoda |
| 2nd Author's Affiliation | Tokyo Institute of Technology(Tokyo Tech) |
| 3rd Author's Name | Atsushi Takahashi |
| 3rd Author's Affiliation | Tokyo Institute of Technology(Tokyo Tech) |
| Date | 2024-02-28 |
| Paper # | VLD2023-104,HWS2023-64,ICD2023-93 |
| Volume (vol) | vol.123 |
| Number (no) | VLD-390,HWS-391,ICD-392 |
| Page | pp.pp.30-35(VLD), pp.30-35(HWS), pp.30-35(ICD), |
| #Pages | 6 |
| Date of Issue | 2024-02-21 (VLD, HWS, ICD) |