| Presentation | 2024-02-29 [Memorial Lecture] Modeling of Tamper Resistance to Electromagnetic Side-channel Attacks on Voltage-scaled Circuits Kazuki Minamiguchi, Yoshihiro Midoh, Noriyuki Miura, Jun Shiomi, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The threat of information leakage by Side-Channel Attacks (SCAs) using ElectroMagnetic (EM) leakage is becoming more and more prominent for crypto circuits. This paper models tamper resistance to EM SCAs on voltage-scaled crypto circuits. It is well know that if the supply voltage is donwscaled, attackers need to acquire more EM traces to extract secret key information in crypto circuits. Therefore, crypto circuits can process more data safely. However, their supply voltage dependence is not fully studied. This paper thus firstly models voltage dependence of the strength in the EM emission from crypto circuits. Then, this paper models the tamper resistance which analytically expresses the relationship between the necessary number of EM traces and the supply voltage. This helps consider to optimize the trade-off relationship between encryption performance and tamper resistance to the information leakage. The proposed models are validated by measurement results using an Advanced Encryption Standard (AES) circuit with a 180-nm process technology. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Electromagnetic leakage / side-channel attack / voltage-scaled circuit design |
| Paper # | VLD2023-117,HWS2023-77,ICD2023-106 |
| Date of Issue | 2024-02-21 (VLD, HWS, ICD) |
| Conference Information | |
| Committee | VLD / HWS / ICD |
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| Conference Date | 2024/2/28(4days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Shigetoshi Nakatake(Univ. of Kitakyushu) / Daisuke Suzuki(Mitsubishi Electric) / Makoto Ikeda(Univ. of Tokyo) |
| Vice Chair | Yuichi Sakurai(Hitachi) / Yuichi Hayashi(NAIST) / Toru Akishita(Sony Semiconductor Solutions) / Hayato Wakabayashi(Sony Semiconductor Solutions) |
| Secretary | Yuichi Sakurai(Socionext) / Yuichi Hayashi(Hirosaki Univ.) / Toru Akishita(Sony Semiconductor Solutions) / Hayato Wakabayashi(AIST) |
| Assistant | Takuma Nishimoto(Hitachi) / / Ryo Shirai(Kyoto Univ.) / Jun Shiomi(Osaka Univ.) / Takeshi Kuboki(Sony Semiconductor Solutions) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Hardware Security / Technical Committee on Integrated Circuits and Devices |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | [Memorial Lecture] Modeling of Tamper Resistance to Electromagnetic Side-channel Attacks on Voltage-scaled Circuits |
| Sub Title (in English) | |
| Keyword(1) | Electromagnetic leakage |
| Keyword(2) | side-channel attack |
| Keyword(3) | voltage-scaled circuit design |
| 1st Author's Name | Kazuki Minamiguchi |
| 1st Author's Affiliation | Osaka University(Osaka Univ.) |
| 2nd Author's Name | Yoshihiro Midoh |
| 2nd Author's Affiliation | Osaka University(Osaka Univ.) |
| 3rd Author's Name | Noriyuki Miura |
| 3rd Author's Affiliation | Osaka University(Osaka Univ.) |
| 4th Author's Name | Jun Shiomi |
| 4th Author's Affiliation | Osaka University(Osaka Univ.) |
| Date | 2024-02-29 |
| Paper # | VLD2023-117,HWS2023-77,ICD2023-106 |
| Volume (vol) | vol.123 |
| Number (no) | VLD-390,HWS-391,ICD-392 |
| Page | pp.pp.99-99(VLD), pp.99-99(HWS), pp.99-99(ICD), |
| #Pages | 1 |
| Date of Issue | 2024-02-21 (VLD, HWS, ICD) |