Summary
International Technical Conference on Circuits/Systems, Computers and Communications
2008
Session Number:P1
Session:
Number:P1-7
A 1MHz High Efficient, Two-Stage Interleaved Synchronous Buck CMOS DC-DC Converter
Jong-Ha Park, Hoon Kim, Hee-Jun Kim, Gyun Chae,
pp.-
Publication Date:2008/7/7
Online ISSN:2188-5079
Summary:
This paper presents a high efficient 3.3 - 1V two-stage interleaved synchronous buck CMOS DC-DC converter designed with standard CMOS 0.35μm process parameter. The proposed circuit has a low ouput voltage ripple. To reduce the ouput voltage ripple, the duty cycle of the interleaved converter is fixed as D=0.5 by an input stage buck converter. It causes the best ripple cancelation of the output current ripple. The proposed circuit was simulated by HSPICE and the simulation results show that the efficiency of the proposed converter is more than 85% in the load current range of 125 - 400mA, and the peak-to-peak output voltage ripple is measured as 10 mV with the 1μF external output capacitor. From these results, the proposed circuit is adequate for the battery-operated system