Summary
International Technical Conference on Circuits/Systems, Computers and Communications
2008
Session Number:P1
Session:
Number:P1-22
Design of Clock Gears for Low-power Media Bus
Yong-Hwan Lee, Hoon-Ju Chung, Chang-Gu Rho,
pp.-
Publication Date:2008/7/7
Online ISSN:2188-5079
Summary:
In this paper, we design and verify a clock gear for low-power media bus. An audio applications use various sample rates i.e. 4K family (4, 8, 16, 24, 32, 48, 96 KHz) and 11.025K family (11.025, 22.05, 44.1, 88.2 KHz) frequencies. To support those frequencies, many clock sources are required and the fixed frequency of clock source often results in unnecessary power dissipation. Clock gears can simplify the problem related to clock. There is no need to use many clock sources but only one clock source can generate various clock frequencies. Clock gears can dynamically change the frequency of clock according to the amount of data for optimal power consumption. The Clock gear is designed in Verilog HDL and simulated. During simulation, the frequency of clock is calculated and automatically checked by a result verification program to validate the function of the clock gears