Summary
International Technical Conference on Circuits/Systems, Computers and Communications
2008
Session Number:P1
Session:
Number:P1-16
Logarithmic and Antilogarithmic Circuit with Gate - to - Substrate Biasing Technique
Sanchai Harnsoongnoen, Chiranut Sa-ngiamsak, Poonsak Intarakul, Rardchawadee Silapunt,
pp.-
Publication Date:2008/7/7
Online ISSN:2188-5079
Summary:
This is a report on a high frequency response and low static power dissipation logarithmic and antilogarithmic circuit generated by a single MOS transistor operating in a weak inversion mode with the gate?to?substrate (G-B) biasing technique. A comparison of the simulation results and the measurements is shown in this paper. The simulation results are generated by PSPICE with AMS 0.8μm technology. The simulation results are also compared with the case of conventional biasing technique. The comparison intriguingly reveals that the frequency response of the proposed circuit is 45k times higher than that of the conventional circuit; its static power consumption is zero watt due to none of biasing current to operate the device when there is no input signal.