Summary
International Symposium on Electromagnetic Compatibility
2009
Session Number:23S3
Session:
Number:23S3-3
Immunity Estimation to Electrostatic Discharge by Circuit Simulation and Conducted Immunity Measurement of Ics
Y. Shiraki,
pp.701-704
Publication Date:2009/7/20
Online ISSN:2188-5079
Summary:
The author proposed an immunity estimation technique to electrostatic discharge (ESD) in the early design stage. The immunity estimation technique was applied to the immunity estimation of ICs on printed wiring boards (PWBs). It consists of a conducted immunity measurement of ICs and a circuit simulation. In the conducted immunity measurement, conducted noise from an ESD-gun is directly injected between a power terminal and a ground terminal of ICs and increased up to a malfunction of the IC. The input voltage at the IC terminals is measured when the IC malfunctions. In the circuit simulation, equivalent circuits are created by modeling the structure of the ESD-gun and the PWBs. The equivalent circuits were analyzed by the circuit simulation and calculated induced voltages between a power layer and a ground layer of the PWBs. Finally, threshold failure levels of the ICs on the printed wiring boards to ESD were defined as ratio of the input voltage in the conducted immunity measurement and the induced voltage in the circuit simulation. The results of the immunity estimation technique were verified experimentally.