Summary
International Technical Conference on Circuits/Systems, Computers and Communications
2016
Session Number:M2-2
Session:
Number:M2-2-1
High Performance and Low Design Cost TLB for MIPS32 Processor
Takahiro Sasaki, Gun Muto, Yuki Fukazawa, Toshio Kondo ,
pp.141-144
Publication Date:2016/7/10
Online ISSN:2188-5079
Summary:
TLB (Translation Lookaside Buffer) is one of the key components which affects performance and circuit scale. To improve performance of TLB, it is effective to increment the number of entries. However, because MIPS32 processor adopts CAM based TLB, increasing TLB entry causes serious enlargement of circuit scale. Furthermore, MIPS32 ISA limits the TLB entries up to 64. This paper proposes two methods to break the limitation; one is new approach to implement TLB using RAM for small footprint, and another is adopting a dynamic code analyzer to handle more than 64 TLB entries while keeping binary compatibility. According to the evaluation results, the proposed approach improves hit rate by 20% at the maximum, 6% in average, and reduces area by 29%.