Summary
International Symposium on Nonlinear Theory and its Applications
2008
Session Number:B4L-D
Session:
Number:B4L-D2
Stochastic Modeling and Verification of a 0.35 μm CMOS Chaos-based True Random Number Generator
Fabio Pareschi, Riccardo Rovatti, Gianluca Setti,
pp.-
Publication Date:2008/9/7
Online ISSN:2188-5079
Summary:
In this paper we present a high-level stochastic model for a true random number generator designed in 0.35 μm CMOS technology, which internally exploits a pipeline analog-to-digital converter modified to operate as a set of chaotic maps. The model is tuned on Monte Carlo circuit-level simulations to include the non-idealities of the designed circuit in the chaotic map model. The parameters of the model are then verified with a comparison between results of NIST statistical tests of the output streams given both by the stochastic model and by the implemented circuit. Once properly tuned, such model actually defines a macro-block which can be exploited for fast generation of a random bit stream necessary in the simulation of others circuits/systems.