Summary
International Technical Conference on Circuits/Systems, Computers and Communications
2016
Session Number:T3-2
Session:
Number:5151
Communication Aware Compiler for Mesh-Structured Reconfigurable Processors on Single/Multi Chip
Yi Lu, Qinhao Wang, Amir Masoud Gharehbaghi, Masahiro Fujita ,
pp.605-608
Publication Date:2016/7/10
Online ISSN:2188-5079
Summary:
Many-core system performance is still underutilized in many cases. The program optimization on highly parallel systems is hard and usually done manually. The inter-core data transfer delay highly affects the system performance in deep sub-micron age. To overcome these problem, in this paper, we propose an integer linear programming (ILP) based method to analyze and optimize a program running on a mesh-structured processors array. The proposed model includes communication-aware operation binding and mapping. as well as data transfer routing. With this flexible ILP based formulation, optimized binding, mapping and routing is determined for a given program on the target architecture. Our ILP based formulation can also be used for high level ECO while performing high level synthesis.