Summary
International Technical Conference on Circuits/Systems, Computers and Communications
2016
Session Number:T2-2
Session:
Number:4785
Implementation of Low Power Consumption of Neuromorphic Devices
Takahiro Toizumi, Yoshiki Sasaki, Katsutoshi Saeki ,
pp.499-502
Publication Date:2016/7/10
Online ISSN:2188-5079
Summary:
When the large scale Artificial Neural Network is constructed, it is desirable that power consumption of a neuromorphic device is low power consumption. In this paper, we reduce the gate voltage of NMOS as a negative resistance device.As a result, it is clearly shown that power consumption of a neuromorphic device is reduced to about 16.6% when compared with the previous model.