Summary
International Technical Conference on Circuits/Systems, Computers and Communications
2016
Session Number:P3
Session:
Number:P3-1
Analysis of I/0 Clamp, Power Clamp ESD Protection Circuit
Byung-Seok Lee, Jun-Geol Park, Chung-Kwang Lee, Kyoung-il Do, Yong-Seo Koo ,
pp.995-998
Publication Date:2016/7/10
Online ISSN:2188-5079
Summary:
This paper presents a ESD protection device for I/O clamp and power clamp. The proposed ESD protection devices has a fast turn on time, low trigger voltage, and high holding voltage characteristics than conventional ESD protection device. The proposed device was analyzed to figure out electrical characteristics and tolerance robustness in term of individual design parameters (D1, D2, D3). They are investigated by using the Synopsys TCAD simulator. The results show that the STNMOS (Substrate Triggered NMOS) device has lower trigger voltage 4.8V compared to the conventional GGNMOS. In addition the proposed a novel SCR (Silicon Controlled Rectifier) - based ESD (Electrostatic Discharge) protection device for power clamp. The proposed device has a higher holding voltage characteristic than conventional SCR. These characteristics enable to have latch-up immunity under normal operating conditions as well as superior full chip ESD protection. As a result of simulation, holding voltage increased with different design parameters. The holding voltage of the proposed device changes from 3.3V to 7.9V.