Summary
International Technical Conference on Circuits/Systems, Computers and Communications
2008
Session Number:P2
Session:
Number:P2-26
A Design of High-Speed 1-Bit Full Adder Cell using 0.18um CMOS Process
Young Woon Kim, Hae Jun Seo, Tae Won Cho,
pp.-
Publication Date:2008/7/7
Online ISSN:2188-5079
Summary:
With the recent development of portable system such as mobile communication and multimedia. Full adders are important components in applications such as digital signal processors and microprocessors. We propose a new full adder with modified version of conventional Ratioed logic and Pass Transistor logic. The proposed adder has the advantages over the conventional logic. The delay time is improved by 17% comparing to the average value and PDP(Power Delay Product) is improved by 19% comparing to the average value. The physical design has been evaluated using HSPICE.