Summary
International Technical Conference on Circuits/Systems, Computers and Communications
2008
Session Number:P2
Session:
Number:P2-22
A New Culling Scheme for Low Power 3D Graphic Processors
Chanho Lee, Kyeongeun Choi,
pp.-
Publication Date:2008/7/7
Online ISSN:2188-5079
Summary:
Recently, portable devices employ applications using 3D graphics such as 3D games and 3D navigations. The portable devices require small area and low power consumption. We propose an efficient culling scheme for low power 3D graphics processors. The proposed culling scheme consists of the selection and back-face culling in the geometry engine and the elimination of pixels outside in the rasterizer engine. The new scheme reduced both the hardware complexity and the number of operation cycles of culling operations. We design a 3D graphic pipeline using Verilog-HDL according to the proposed scheme, and verify it on an FPGA prototyping board. The latency of the proposed architecture is reduced by 15 cycles and the gate count of the synthesized result is reduced by 8%.