Summary
International Technical Conference on Circuits/Systems, Computers and Communications
2016
Session Number:M3-3
Session:
Number:M3-3-1
A Cost-Efficient Tuner Design for Digital TV Receiver
Shih-Chang Hsia, Po-Yu Hsiao, Ming-Hwa Sheu, Hsin-Hsien Huang ,
pp.311-314
Publication Date:2016/7/10
Online ISSN:2188-5079
Summary:
In this study, a single-chip is designed with MOS techniques for the digital TV tuner. The chip consists of the modules of low noise amplifier (LNA), RF mixer, digital voltage control oscillator, and polyphase filter. The tuner is designed with the structure of a single conversion by mixing the Quadrature local signal with polyphase filter. The frequency band is designed from 530 MHz to 602 MHz for DTV channels in Taiwan. The gain of the entire tuner can be over 32 dBm, and the image rejection ratio (IRR) of the tuner is above 30 dBm. The local oscillator built-in digital-to-analog converter can be directly controlled by a digital code to select the TV channel. The silicon chip had been designed with a full-custom layout, where the chip size and core size is about 0.497 and 0.1095 mm2, respectively, when implemented by TSMC 0.18µm CMOS process. The maximum power dissipation is about 136.7 mW when the chip works 3.3V.