Summary
International Technical Conference on Circuits/Systems, Computers and Communications
2016
Session Number:M1-5
Session:
Number:M1-5-2
High Level Synthesis of Neville Interpolation on an Embedded FPGA Platform using SDSoC
Kyeong-Bin Park, Jung-Hyun Hong, Ki-Seok Chung ,
pp.77-78
Publication Date:2016/7/10
Online ISSN:2188-5079
Summary:
Today, high-level synthesis (HLS) has emerged as a widely used method for various digital systems. In this paper, we propose a the line interpolator implemented on Xilinx Zynq SoC using a high-level synthesis tool called Software-Defined SoC (SDSoC). There are lots of iterative calculations in the line interpolation algorithm; therefore, the hardware acceleration is preferred over the software-only implementation. We implement the Neville interpolation algorithm and apply the loop unrolling and pipelining techniques to fully utilize the target FPGA. When the utilization techniques are applied, the area is increased, but the total execution time is reduced by 10 times. The proposed implementation using SDSoC shows better performance compared to the software-only one, and fast design space exploration is achieved using HLS compared to the conventional RTL design.