number | title/author |
---|---|
M1-2-1 | Deadline-Constrained Static Mapping of Parallelizable Tasks on Manycore Architectures Yining Xu, Ittetsu Taniguchi, Hiroyuki Tomiyama , |
M1-2-2 | Design and Evaluation of MTJ-based Standard Cell Memory Junya Akaike, Masaru Kudo, Kimiyoshi Usami , |
M1-2-3 | Low-power Standard Cell Memory using Silicon-on-Thin-BOX (SOTB) and Body-bias Control Yusuke Yoshida, Masaru Kudo, Kimiyoshi Usami , |