number | title/author |
---|---|
C3L-C1 | An Error Bound of a Solution for Linear Passive DC Circuits Without Constructing Circuit Equations Tetsuo Nishi, Shin’ichi Oishi, Yusuke Nakaya, |
C3L-C2 | A Clock-Period Comparison ADPLL with a Linearity Improved DCO Yukinobu Makihara, Masayuki Ikebe, Junichi Motohisa, Eiichi Sano, |
C3L-C3 | Experimental Study of Gaussian Noise Generation Using a CMOS PLL Akio Takada, Tetsuro Endo, |
C3L-C4 | Analysis of Paralleled Switched-Capacitor DC-DC Converters with Voltage-Controlled Switching Hiroyuki Nakamura, Toshimichi Saito, |