Information and Systems-Software Science(Date:2000/06/23)

Presentation
表紙

,  

[Date]2000/6/23
[Paper #]
目次

,  

[Date]2000/6/23
[Paper #]
Efficient algorithm of packet destination addresses generation based on logically segmented LRU stack management

Michiyo MATSUDA,  Kaori MURANAKA,  Masaki AIDA,  

[Date]2000/6/23
[Paper #]SSE2000-50
Internet Traffic Characteristics at the Highest Layer for Traffic Modeling

Kaori Muranaka,  Tetsuya Abe,  Masaki Aida,  

[Date]2000/6/23
[Paper #]SSE2000-51
ZL-RED mechanism for Fairness Improvement between TCP Reno and Vegas

Kenji Kurata,  Go Hasegawa,  Masayuki Murata,  

[Date]2000/6/23
[Paper #]SSE2000-52
A Study of Load Balancing for IP Traffic Engineering

Toshio Soumiya,  Koji Nakamichi,  Kenya Takashima,  Nobuyuki Kobayashi,  

[Date]2000/6/23
[Paper #]SSE2000-53
A Study on Load Balancing Method with Explicit Routing in MPLS Networks

Takashi Miyamura,  Takashi Kurimoto,  Michihiro Aoki,  Naoaki Yamanaka,  

[Date]2000/6/23
[Paper #]SSE2000-54
SSE2000-55 Symmetric Routing and Wavelength Assignment algorithm for two Regular Topology All Optical Networks

Sugang Xu,  Kaoru SEZAKI,  

[Date]2000/6/23
[Paper #]SSE2000-55
SSE2000-56 Contention-based Reservation Protocol Using a Counter for Detecting a Source Conflict in WDM Single-hop Optical Network with Non-equivalent Distance

Makoto Sakuta,  Yoshiyuki Nishino,  Iwao Sasase,  

[Date]2000/6/23
[Paper #]SSE2000-56
Performance Evaluation of VC-merge capable ATM switch with input and output buffer

Kenji Sakamoto,  Yoshiyuki Nishino,  Iwao Sasase,  

[Date]2000/6/23
[Paper #]SSE2000-57
SSE2000-58 A Shared Knockout Switch for Reduction of Hardware

Yoshiyuki Nishino,  Iwao Sasase,  

[Date]2000/6/23
[Paper #]SSE2000-58
SSE2000-59 Evaluation of a Network Processor for Very High-speed Transmission Lines

Hideyuki Shimonishi,  Tutomu Murase,  

[Date]2000/6/23
[Paper #]SSE2000-59
A Study on the Number of SVC Subscriber in an ATM Node

Takao Matsuda,  Miki Hirano,  

[Date]2000/6/23
[Paper #]SSE2000-60
Reliability evaluation for the next generation node architecture

Hiroyuki Funakoshi,  Hiroshi Niitsu,  Hiroshi Sunaga,  

[Date]2000/6/23
[Paper #]SSE2000-61
[OTHERS]

,  

[Date]2000/6/23
[Paper #]