Information and Systems-Speech(Date:2003/06/20)

Presentation
A Construction Method of Path Delay Faults Detectable Sequential Circuits

Genta SAKUMA,  Hiroyuki SHIMAJIRI,  Takeo YOSHIDA,  

[Date]2003/6/20
[Paper #]DSP2003-69
RTL Design for High Throughput Pipelined CMA Adaptive Equalizer

Masashi MIZUNO,  James OKELLO,  Hiroshi OCHI,  

[Date]2003/6/20
[Paper #]DSP2003-70
On a software system generating hardware Ips for speech recognition

Atsuya KAGEYAMA,  Shingo YOSHIZAWA,  Noboru HAYASAKA,  Yoshikazu MIYANAGA,  

[Date]2003/6/20
[Paper #]DSP2003-71
Hardware Implementation of a Noise Robust Speech Recognition System Using RSF/DRA Technique

Shingo YOSHIZAWA,  Naoya WADA,  Noboru HAYASAKA,  Yoshikazu MIYANAGA,  

[Date]2003/6/20
[Paper #]DSP2003-72
奥付

,  

[Date]2003/6/20
[Paper #]
複写される方へ

,  

[Date]2003/6/20
[Paper #]
<<12 21-26hit(26hit)