| Presentation | 2003/6/20 Hardware Implementation of a Noise Robust Speech Recognition System Using RSF/DRA Technique Shingo YOSHIZAWA, Naoya WADA, Noboru HAYASAKA, Yoshikazu MIYANAGA, |
|---|---|
| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this report, we describe a novel method focusing on time variation and dynamic range of speech feature parameters and introduce a hardware based speech recognition system using this technique. RSF (Running Spectrum Filtering) applies the time variation of feature parameters to FIR filtering. DRA (Dynamic Range Ad-justment) normalizes the maximum amplitudes of the waveforms. The combination of two methods improves noise robust recognition performance compared with conventional methods. However, the realization of the proposed method in software processing is quite difficult because recognition processing starts after speech analysis processing. Therefore the hardware system accelerates recognition processing remarkably by using parallel processing, fixed-point representation and data scaling. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | speech recognition / noise robust / parallel processing / VLSI / fixed-point arithmetic |
| Paper # | DSP2003-72 |
| Date of Issue |
| Conference Information | |
| Committee | DSP |
|---|---|
| Conference Date | 2003/6/20(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Digital Signal Processing (DSP) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Hardware Implementation of a Noise Robust Speech Recognition System Using RSF/DRA Technique |
| Sub Title (in English) | |
| Keyword(1) | speech recognition |
| Keyword(2) | noise robust |
| Keyword(3) | parallel processing |
| Keyword(4) | VLSI |
| Keyword(5) | fixed-point arithmetic |
| 1st Author's Name | Shingo YOSHIZAWA |
| 1st Author's Affiliation | Graduate School of Engineering, Hokkaido University() |
| 2nd Author's Name | Naoya WADA |
| 2nd Author's Affiliation | Graduate School of Engineering, Hokkaido University |
| 3rd Author's Name | Noboru HAYASAKA |
| 3rd Author's Affiliation | Graduate School of Engineering, Hokkaido University |
| 4th Author's Name | Yoshikazu MIYANAGA |
| 4th Author's Affiliation | Graduate School of Engineering, Hokkaido University |
| Date | 2003/6/20 |
| Paper # | DSP2003-72 |
| Volume (vol) | vol.103 |
| Number (no) | 147 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |