Presentation 2003/6/20
On a software system generating hardware Ips for speech recognition
Atsuya KAGEYAMA, Shingo YOSHIZAWA, Noboru HAYASAKA, Yoshikazu MIYANAGA,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) In this report, we have developed a CAD system which can design hardware Ips on a HMM based speech recognition system which has the specifications required by users. The users decide the parameters of HMM model states and vector dimensions, etc. by using graphical user interface (GUI). This CAD system generates the Verilog-HDL source codes corresponding to its parameters. Moreover, this CAD has the functions of generating the HMM model parameters, evaluting speech recognition experiments on PC and circuit simulations. Using this CAD, we have investigeted the relations among the number of training speakers, recognition performance and system specs.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) IP / HMM / isolated word recognition / graphical user interface / Verilog-HDL
Paper # DSP2003-71
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Conference Information
Committee DSP
Conference Date 2003/6/20(1days)
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Registration To Digital Signal Processing (DSP)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) On a software system generating hardware Ips for speech recognition
Sub Title (in English)
Keyword(1) IP
Keyword(2) HMM
Keyword(3) isolated word recognition
Keyword(4) graphical user interface
Keyword(5) Verilog-HDL
1st Author's Name Atsuya KAGEYAMA
1st Author's Affiliation Graduate School of Engineering, Hokkaido University()
2nd Author's Name Shingo YOSHIZAWA
2nd Author's Affiliation Grasdate School of Engineering, Hokkaido University
3rd Author's Name Noboru HAYASAKA
3rd Author's Affiliation Grasdate School of Engineering, Hokkaido University
4th Author's Name Yoshikazu MIYANAGA
4th Author's Affiliation Grasdate School of Engineering, Hokkaido University
Date 2003/6/20
Paper # DSP2003-71
Volume (vol) vol.103
Number (no) 147
Page pp.pp.-
#Pages 6
Date of Issue