Presentation 2003/6/20
A Construction Method of Path Delay Faults Detectable Sequential Circuits
Genta SAKUMA, Hiroyuki SHIMAJIRI, Takeo YOSHIDA,
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Abstract(in English) In this paper, we show a construction method of sequential circuits which can detect path delay faults. The proposed method is applied a two-pattern test for path delay faults. Path delay faults have an effect on a value of a register of a sequential circuit. Therefore it is possible to detect path delay faults to observe the value of the register in the sequential circuit. In this paper, we examine the detection condition for path delay faults. We propose a state assignment method which satisfies the detection condition. We show a design example of path delay faults detectable sequential circuits which is adopted the proposed method.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) path delay fault / fault detection / wiring delay / state assignment
Paper # DSP2003-69
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Committee DSP
Conference Date 2003/6/20(1days)
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Registration To Digital Signal Processing (DSP)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Construction Method of Path Delay Faults Detectable Sequential Circuits
Sub Title (in English)
Keyword(1) path delay fault
Keyword(2) fault detection
Keyword(3) wiring delay
Keyword(4) state assignment
1st Author's Name Genta SAKUMA
1st Author's Affiliation Department of Information Engineering, Faculty of Engineering, University of the Ryukyus()
2nd Author's Name Hiroyuki SHIMAJIRI
2nd Author's Affiliation Department of Information Engineering, Faculty of Engineering, University of the Ryukyus
3rd Author's Name Takeo YOSHIDA
3rd Author's Affiliation Department of Information Engineering, Faculty of Engineering, University of the Ryukyus
Date 2003/6/20
Paper # DSP2003-69
Volume (vol) vol.103
Number (no) 147
Page pp.pp.-
#Pages 6
Date of Issue