Electronics-Integrated Circuits and Devices(Date:2009/12/07)

Presentation
Development of a Stream Cipher Engine Chip

Takumi ISHIHARA,  Harunobu UCHIUMI,  Yusuke Osumi,  Masa-aki FUKASE,  Tomoaki SATO,  

[Date]2009/12/7
[Paper #]ICD2009-94
A New VLSI System Architecture Mimicking the Processing in the Mind

Tadashi SHIBATA,  

[Date]2009/12/7
[Paper #]ICD2009-95
History and Technology Trends of Si RF Analog LSI Developments : Emergence of New-Type Circuit Designers

Tsuneo TSUKAHARA,  

[Date]2009/12/7
[Paper #]ICD2009-96
A remote optically reconfigurable gate array with 4 configuration contexts

Yumiko UENO,  Minoru WATANABE,  

[Date]2009/12/7
[Paper #]ICD2009-97
Wide Swing, Low Gain Error Voltage Buffer with Adaptive Biasing for Improving Slew-rate

Jagatjyoti GHIMIRE,  Cong-Kha PHAM,  

[Date]2009/12/7
[Paper #]ICD2009-98
Design of High-Resolution Continuous-Time Bandpass Delta-Sigma AD Modulator

Haijun Lin,  Atsushi MOTOZAWA,  RE Pascal LO,  Kunihiko IIZUKA,  Haruo KOBAYASHI,  Hao SAN,  Nobukazu TAKAI,  

[Date]2009/12/7
[Paper #]ICD2009-99
Sturdy-MASH-type ΔΣAD Modulator with Wide Dynamic Range

Takafumi Yamada,  Hajime Konagaya,  Hao San,  Haruo Kobayashi,  

[Date]2009/12/7
[Paper #]ICD2009-100
Non-binary SAR ADC with Digital Compensation for Comparator Offset Effects

Tomohiko OGAWA,  Tatsuji MATSUURA,  Haruo KOBAYASHI,  Nobukazu TAKAI,  Masao HOTTA,  Hao SAN,  

[Date]2009/12/7
[Paper #]ICD2009-101
A Simple High Efficiency DC-DC Converter Adaptive to Input Voltage and Load Current

Pin ZHANG,  Cong-Kha PHAM,  

[Date]2009/12/7
[Paper #]ICD2009-102
Inductor Design of 20-V Boost Converter for Low Power 3D Solid State Drive

Tadashi YASUFUKU,  Koichi ISHIDA,  Shinji MIYAMOTO,  Hiroto NAKAI,  Makoto TAKAMIYA,  Takayasu SAKURAI,  Ken TAKEUCH,  

[Date]2009/12/7
[Paper #]ICD2009-103
Bandwidth Enhancement for TIA with Mutually Coupled Inductors

Yoshihiro OKUMURA,  Makoto NAKAMURA,  Keiji KISHINE,  Akira TSUCHIYA,  Hidetoshi ONODERA,  

[Date]2009/12/7
[Paper #]ICD2009-104
誘導結合通信を用いた低消費電力・高性能三次元プロセッサの開発 : 90nm CMOSマルチコアプロセッサと65nm CMOS SRAMの三次元システム集積(若手研究会)

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[Date]2009/12/7
[Paper #]ICD2009-105
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[Date]2009/12/7
[Paper #]
奥付

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[Date]2009/12/7
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