| Presentation | 2009-12-15 Non-binary SAR ADC with Digital Compensation for Comparator Offset Effects Tomohiko OGAWA, Tatsuji MATSUURA, Haruo KOBAYASHI, Nobukazu TAKAI, Masao HOTTA, Hao SAN, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper describes techniques for creating a low-power SAR ADC with an error-correcting non-binary successive approximation algorithm : (1) We propose a non-binary SAR ADC with two dynamic comparators; a low-power high-noise comparator for the first conversion stages, and a second comparator with lower noise but higher power consumption for the last stages. Comparator decision errors - due to the high noise of the first conversion stages, and offset mismatch between the two comparators - are digitally corrected by the error-correcting non-binary successive approximation algorithm. (2) For realizing low power consumption, a charge-sharing SAR ADC using a binary successive approximation algorithm would be attractive. However the comparator offset in the ADC degrades the ADC linearity, and this offset is usually calibrated by an analog method. Here we propose a charge-sharing SAR ADC with an error-correcting non-binary algorithm, and with digital correction of comparator offset, so that analog calibration is not required. (3) We also propose a non-binary charge-sharing SAR ADC with two dynamic comparators, which is the combination of (1) and (2). This makes further low power implementation possible without analog calibration. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | SAR ADC / Comparator / Low Power / Redundancy / Digitally-Assisted Analog Technology |
| Paper # | ICD2009-101 |
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| Committee | ICD |
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| Conference Date | 2009/12/7(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Non-binary SAR ADC with Digital Compensation for Comparator Offset Effects |
| Sub Title (in English) | |
| Keyword(1) | SAR ADC |
| Keyword(2) | Comparator |
| Keyword(3) | Low Power |
| Keyword(4) | Redundancy |
| Keyword(5) | Digitally-Assisted Analog Technology |
| 1st Author's Name | Tomohiko OGAWA |
| 1st Author's Affiliation | Dept. of Electronic Engineering, Gunma University() |
| 2nd Author's Name | Tatsuji MATSUURA |
| 2nd Author's Affiliation | Renesas Technology Corp |
| 3rd Author's Name | Haruo KOBAYASHI |
| 3rd Author's Affiliation | Dept. of Electronic Engineering, Gunma University |
| 4th Author's Name | Nobukazu TAKAI |
| 4th Author's Affiliation | Dept. of Electronic Engineering, Gunma University |
| 5th Author's Name | Masao HOTTA |
| 5th Author's Affiliation | Dept. of Information Network Engineering, Tokyo City University |
| 6th Author's Name | Hao SAN |
| 6th Author's Affiliation | Dept. of Information Network Engineering, Tokyo City University |
| Date | 2009-12-15 |
| Paper # | ICD2009-101 |
| Volume (vol) | vol.109 |
| Number (no) | 336 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |