Summary
International Symposium on Nonlinear Theory and its Applications
2017
Session Number:A3L-A
Session:
Number:A3L-A-6
Delta Sigma Domain LDPC Decoder Based on Min-Sum Algorithm
Akiyoshi Yasuda, Hisato Fujisaka, Masaru Fukushima, Takeshi Kamio,
pp.213-216
Publication Date:2017/12/4
Online ISSN:2188-5079
Summary:
Combination of interleaving and random error correction code is effective as a measure against burst error when power line is used for communication between ECUs in a car. However, since many ECUs are mounted in a car, miniaturization and cost reduction are required for reliable communication circuits. In this study, we construct an LDPC decoder circuit that performs error correction in the delta sigma domain based on the Min-Sum algorithm and attempts to downsize the circuit.