Summary
International Technical Conference on Circuits/Systems, Computers and Communications
2008
Session Number:P1
Session:
Number:P1-26
Area Efficient H.264/AVC CAVLC Decoder Architecture
Byung-Sik Choi, Jong-Yeol Lee,
pp.-
Publication Date:2008/7/7
Online ISSN:2188-5079
Summary:
In this paper, we propose an area-efficient VLSI architecture of H.264/AVC CAVLC decoder. In the proposed architecture, we reduce the decoder area by rearranging the lookup tables. We also save the bus area and cycles by delaying T1s decoding to the final reordering step which is performed in output buffer. To remove the overlapped logics we combine a controller and a barrel shifter. By using the proposed architecture, we can reduce the area by about 30% compared with previous work. We design the proposed decoder using Verilog HDL and synthesize using 0.35μm standard cell library. We verify the proposed architecture by simualation that the designed decoder can run at the frequency of 50Mhz.