Summary
International Technical Conference on Circuits/Systems, Computers and Communications
2008
Session Number:H3
Session:
Number:H3-2
A Design of Low-Power Frequency Synthesizer for GPS Application using Multiple Reference Clocks in 0.18μm CMOS Technology
YoungGun Pu, Jun-Gi Jo, Changsik Yoo, Dojin Park, Seong-Eon Park, Suk-Joong Lee, Kang-Yoon Lee,
pp.-
Publication Date:2008/7/7
Online ISSN:2188-5079
Summary:
This paper presents a low power CMOS frequency synthesizer for GPS application that can support multiple reference clocks. The frequency synthesizer has fractional-N phase locked loop structure with sigma-delta modulator to allow multiple reference clock frequencies. The measured phase noise is -126dBc/Hz at 1MHz offset from the carrier. This chip is fabricated with 0.18um CMOS technology, and the die area of the frequency synthesizer is 1.1mm x 1.05mm. The power consumption is 18mW at 1.8V supply voltage.