Summary
International Technical Conference on Circuits/Systems, Computers and Communications
2008
Session Number:D3
Session:
Number:D3-4
Recovery Scheme to Reduce Latency of Miss-Prediction for Superscalar Processor using L1 Recovery Cache
JiongYao Ye, Takahiro Watanabe,
pp.-
Publication Date:2008/7/7
Online ISSN:2188-5079
Summary:
A branch prediction is indispensable to modern superscalar processors for high performance. Although it has great possibility to improve performance, the advantage may be lost due to miss-prediction. To reduce such a branch miss-prediction penalty, finer recovery mechanisms are needed. One of those mechanisms is a RcB (recovery buffer), which preserves instructions to be restarted when miss-prediction occurs. But RcB cannot recover instructions issued out of order for a superscalar processor. This paper proposes a L1 recovery cache embedded in a superscalar processing, RcC for short, which overcomes weakness of RcB and can recover instructions issued out of order so that recovery penalty is reduced. Our proposed L1 RcC scheme can work supplementing the conventional 1-bit dynamic branch predictor used in a superscalar processor, so that miss-prediction penalty can be effectively reduced.