Summary
International Technical Conference on Circuits/Systems, Computers and Communications
2008
Session Number:E1
Session:
Number:E1-2
Flexible Multi-IP Verification Methodology Based on an FPGA Platform
Jin Woo Song, Ki-Seok Chung,
pp.-
Publication Date:2008/7/7
Online ISSN:2188-5079
Summary:
It is well-known that in ASIC designs, verification is more difficult and time consuming than design itself. As the number of IPs in an SoC design increases, verifying multiple IPs together is really important to reduce time-to-market. In this paper, we propose a novel SoC platform based verification methodology which tests multiple IPs together using a single testbench. We’ve found that commercially available SoC platform such as Altera Cyclone, Xilinx Spartan FPGA provides excellent environment in verifying the functionalities of mutually interactive multiple IPs with very low cost. In our methodology, Only FPGA is used mainly for verification purposes. We program the softcore CPU, Bus Architecture and other peripherals into the FPGA, which will execute C-based testbench and mutually interactive IPs are also programmed into the FPGA device. We implement a set of tools which consists of a communication interface and a wrapper generator which will automatically connect Bus architecture and the IP module together. Using this platform, we have verified up to 5 IPs together successfully, but we can verify more IPs together easily. Time and effort to verify complex IPs have been significantly reduced using this methodology.