Summary
International Technical Conference on Circuits/Systems, Computers and Communications
2008
Session Number:D4
Session:
Number:D4-1
Low Cost PLD with High Speed Partial Reconfiguration
Naoki Hirakawa, Masanori Yoshihara, Masayuki Sato, Kazuya Tanigawa, Tetsuo Hironaka,
pp.-
Publication Date:2008/7/7
Online ISSN:2188-5079
Summary:
Field Programmable Gate Arrays (FPGAs) have been used for implementing various applications. But the switch matrix occupies a significantly large area in FPGA. And configuration speed of FPGA is slow. So, we proposed MPLD as a new Programmable Logic Device (PLD). MPLD has no switch matrix, and partial reconfiguration is easy and fast because configuration method is same as write access of the conventional parallel memory. In this paper, we present MPLD and evaluation results of the prototype MPLD chip.